1. Technical Field
The present invention relates generally to phase locked loops and, in particular, to reducing phase locked loop (PLL) phase lock time.
2. Description of the Related Art
A phase locked loop (PLL) is a control system that aims to generate an output signal having a phase that is related to the phase of an input (i.e., reference) signal. The lock time of a PLL, also known as phase lock time or frequency acquisition time or settling time, is the time that is takes for the phase of the output of the PLL to be locked to (in synchronization with) the phase of the input of the PLL. Of course, it is advantageous that the lock time of a PLL be as small as possible.
FIG. 1 shows a dual path analog phase locked loop (PLL) 100, in accordance with the prior art. The PLL 100 includes a phase-frequency detector (PFD) 110, a charge pump 1 (CP1) 121, a charge pump 2 (CP2) 122, a divider 130, a voltage controlled oscillator 140, a coarse band controller 150, a capacitor 161, a capacitor 162, and a resistor 170.
In this type of PLL, the integral control path 181 and the proportional control path 182 are implemented separately with two separate charge pumps (CP1 and CP2), filters, and VCO control nodes. In PLL 100, CP1 121 is the integral path charge pump and CP2 122 is the proportional charge pump. The VCO 140 oscillates at a frequency which increases in response to an increase in its input signals. The PFD 110 monitors the phase and frequency difference between its two inputs (the reference clock and the output of the divider 130). The divider 130 divides the frequency of the output of the VCO 140 down to a frequency close to that of the input reference.
In a typical implementation, the proportional control path 182 responds to a phase difference at the input of the PLL 100 by generating a voltage at an input of the VCO 140. If the phase difference goes to zero, then that input of the VCO 140 will go to zero. The integral control path 181 integrates the phase difference at the input of the PLL 100. When the phase difference goes to zero, the integral control path 181 does not go to zero, but maintains its value.
A typical VCO has coarse digitally switched tuning bands in addition to the analog controls. PLL 100 includes a typical automatic coarse band selection circuit, also referred to herein as course band controller 150. Course band controller 150 monitors the integral control voltage, and decrements/increments the coarse controls if the integral control voltage is too high/too low.
The coarse tuning bands are typically used to tune the VCO's frequency to within the range of the fine (analog) integral control. Then the integral control path 181 moves the control voltage until the VCO 140 is oscillating at the correct frequency. Under normal use these bands act as an extension to the range of the integral control path 181 of the PLL 100. A set of comparators in the course band controller 150 detects when the integral control voltage goes above its usable range. If the integral control voltage goes too high/low then the VCO coarse control is incremented/decremented. The coarse controls are increment/decrement until the integral control voltage returns to with its usable range.
FIG. 2 shows an s-domain model 200 of a phase locked loop in accordance with the prior art. For example, the s-domain model 200 can be for PLL 100 shown in FIG. 1. Regarding s-domain model 200, K1 201 and K2 202 represent the proportional and integral path gains, Ko 220 represents the VCO gain, Kd 210 represents the PFD gain, and N 240 represents the divider gain. A combiner 231 includes an inverting input and a non-inverting input. A combiner 232 includes two non-inverting inputs. Equation (1) represents the s-domain transfer function between the phase of the input and output of a type II PLL. A type II PLL is defined as a PLL which includes two integrators in its open loop phase domain transfer function. Equations (2) and (3) relate ωn and ζ to the PLL parameters. In particular, ωn represents the PLL's natural frequency and ζ represents the PLL's damping ratio.
                                          θ            out                                θ                          i              ⁢                                                          ⁢              n                                      =                                            2              ⁢                                                          ⁢              ζ              ⁢                                                          ⁢                              ω                n                            ⁢              s                        +                          ω              n              2                                                          s              2                        +                          2              ⁢                                                          ⁢              ζ              ⁢                                                          ⁢                              ω                n                            ⁢              s                        +                          ω              n              2                                                          (        1        )                                          ω          n                =                                            K              d                        ⁢                          K              o                        ⁢                          K              2                                                          (        2        )                                ζ        =                                            K              1                        2                    ⁢                                                                      K                  d                                ⁢                                  K                  o                                                            K                2                                                                        (        3        )            
It can be show that if ζ>1 then the PLL will not exhibit ringing during frequency/phase acquisition. However if ζ<1, then the PLL can exhibit excessive ringing in its transient settling behavior. For this reason, PLLs are rarely designed with ζ having a value much less than one.
In a dual path PLL (e.g., PLL 100), the proportional control path (e.g., 182) can saturate in the presence of large phase/frequency offsets. If the phase difference at the input of the phase detector is sufficiently large, then the current produced by the charge pump multiplied by the loop filters impedance will be greater that the usable range of the proportional control path.
A saturated proportional control path will have less gain during acquisition than the equivalent unsaturated gain. From Equation (3), we see that if the proportional gain, K1, is reduced, then ζ is also reduced.